Si4710/11-B30
Rev. 1.1
13
Sub Carrier Rejection Ratio
SCR
40
50
dB
Powerup Settling Time
2
110
ms
Input Signal Level
2
V
AI
0.636
V
PK
Frequency Flatness
2
Mono, ?.5 dB,
Df = 75 kHz, 0, 50, 75 祍
pre-emphasis, limiter off
30
15 k
Hz
High Pass Corner Frequency
2
Mono, 3 dB, Df = 75 kHz,
0, 50, 75 祍 pre-emphasis,
limiter off
5
30
Hz
Low Pass Corner Frequency
2
Mono, 3 dB, Df = 75 kHz,
0, 50, 75 祍 pre-emphasis,
limiter off
15 k
16 k
Hz
Audio Imbalance
Mono
1
1
dB
Pilot Modulation Rate Accuracy
2
Df = 68.25 kHz,
Dfpilot = 6.75 kHz, Stereo
10
10
%
Audio Modulation Rate Accuracy
2
Df = 68.25 kHz,
Dfpilot = 6.75 kHz, Stereo
10
10
%
Input Resistance
2
LIATTEN[1:0] = 11
50
60
kW
Input Capacitance
2
10
pF
Table 10. Reference Clock Characteristics
(V
DD
= 2.7 to 5.5 V, V
IO
= 1.5 to 3.6 V, T
A
= 20 to 85 癈, F
RF
= 76108 MHz)
Supported Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
RCLK Frequency Range
1,2
31.130 32.768 40,000
kHz
Frequency Tolerance
1
50
50
ppm
Notes:
1. Guaranteed by characterization.
2. The RCLK frequency divided by an integer number (the prescaler value) must fall in the range of 31,130 to 34,406 Hz.
Therefore, the range of RCLK frequencies is not continuous below frequencies of 311.3 kHz.
Table 9. FM Transmitter Characteristics
1
(Continued)
(Test conditions: V
RF
= 118 dB礦, stereo, Df = 68.25 kHz, Dfpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 祍 pre-emphasis,
unless otherwise specified.
Production test conditions: V
DD
= 3.3 V, V
IO
= 3.3 V, T
A
= 25 癈, F
RF
= 98 MHz.
Characterization test conditions: V
DD
= 2.7 to 5.5 V, V
IO
= 1.5 to 3.6 V, T
A
= 20 to 85 癈, F
RF
= 76108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V
DD
= 3.3 V and 25 癈 unless otherwise stated.
Parameters are tested in production unless otherwise specified.)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in AN383:
Universal Antenna Selection and Layout Guidelines. Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q >
30) shown in Figure 9 on page 14.
2. Guaranteed by characterization.
3. No measurable DfRF/DV
DD
at DV
DD
of 500 mVpk-pk at 100 Hz to 10 kHz.
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